library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity regfile is
	generic
	(
		DATA_WIDTH	: natural  :=	32;
		REG_WIDTH	: natural  :=	5
	);


	port
	(
		-- Input ports
		n0	: in  std_logic_vector(REG_WIDTH-1 downto 0);
		n1	: in  std_logic_vector(REG_WIDTH-1 downto 0);
		nd	: in  std_logic_vector(REG_WIDTH-1 downto 0);
		di	: in  std_logic_vector(DATA_WIDTH-1 downto 0);
		ce	: in  std_logic;
		clk : in  std_logic;
		clrn: in  std_logic;
		
		-- Output ports
		result0	: out std_logic_vector(DATA_WIDTH-1 downto 0);
		result1	: out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end regfile;

architecture rtl_regfile of regfile is
-- register*32
	type reg is array(0 to 31) of std_logic_vector(DATA_WIDTH-1 downto 0);
	shared variable regs: reg;
begin
	process (clk,clrn)
	begin
		if clk'EVENT and clk = '1' then
			if (clrn = '0') then
				for i in 0 to 31 loop
					regs(i) := X"00000000";
				end loop;			
			end if;
			if ce = '1' then
				regs(conv_integer(nd)) := di;			
			end if;			
		end if;
	end process;
	result0 <= regs(conv_integer(n0));
	result1 <= regs(conv_integer(n1));
end rtl_regfile;

